The present invention generally relates to programmable semiconductor memory circuits, and more particularly to a programmable semiconductor memory circuit which has an input circuit with an input threshold value which changes depending on a change of a power source voltage.
As one example of a programmable device, there is a bipolar programmable read only memory (PROM) to which a user can electrically write data. Such a bipolar PROM is popularly used in various fields. Generally, the user writes the data into the bipolar PROM in the following manner. That is, the user selects a memory cell of a memory cell array via an address input circuit by an address which is received from an address driver, and writes the data into the selected memory cell via a write circuit which is driven by a voltage which is received from a programming power source circuit which is used for the programming. In this case, the address input circuit is not limited to a transistor transistor logic (TTL). Recently, a composite circuit such as a complementary metal oxide semiconductor (CMOS) circuit and a bipolar CMOS (BiCMOS) circuit is used for the address input circuit.
Generally, the input threshold value of the CMOS or BiCMOS circuit changes depending on a change of a power source voltage. For this reason, when the CMOS or BiCMOS circuit is used for the address input circuit of the bipolar PROM and the input threshold value of the address input circuit changes due to the change in the power source voltage, an output signal level of the address input circuit is no longer in conformance with a TTL level which is used by the write circuit and a memory cell array of the bipolar PROM. As will be described later, it thus becomes necessary to design the write circuit exclusively for the bipolar PROM which has the CMOS or BiCMOS address input circuit.
FIG.1 shows an essential part of an example of a conventional bipolar PROM. The bipolar PROM generally comprises an address input circuit 2, a memory cell array 3, a programming power source circuit 4, a write circuit 5, and a decoder 6. In a write mode, a predetermined memory cell within the memory cell array 3 is selected by an address which is received from an address driver (writer) 1 via the address input circuit 2 and the decoder 6. The write-in of data to the predetermined memory cell is made via the write circuit 5 which is driven by the programming power source circuit 4.
In the write mode, a power source voltage Vcc is set to 7 V as shown in FIG.2(A) and a write voltage Vw from the programming power source circuit 4 is set to 20 V as shown in FIG.2(B), for example. On the other hand, in the read mode, the power source voltage Vcc is set to 5 V as shown in FIG.2(A) and the write voltage Vw from the programming power source circuit 4 is set to 0 V. The power source voltage Vcc during the write mode is set greater than that during the read mode because in the write mode there is a need to supply a large current to the selected memory cell so as to break and short-circuit a junction of the selected memory cell.
The memory cell array 3 of the bipolar PROM usually employs the TTL. For this reason, the address input circuit 2 is TTL circuit and a PROM writer which programs the bipolar PROM is designed to operate with the TTL level. FIG.3 shows an example of the TTL address input circuit 2. The TTL address input circuit 2 comprises transistors Tr1 through Tr4, resistors r1 through r3, and a diode d which are connected as shown. Vcc denotes the power source voltage and GND denotes the ground voltage. An input threshold value Vth of this TTL address input circuit 2 can be described by Vth=V.sub.BE1 +V.sub.BE2 -V.sub.CE, where V.sub.BE1 denotes a base-emitter voltage of the transistor Tr4, V.sub.BE2 denotes a base-emitter voltage of the transistor Tr2, and V.sub.CE denotes a collector-emitter voltage of the transistor Tr1. Hence, the input threshold value Vth of the address input circuit 2 will not change even when the power source voltage Vcc changes.
When employing the BiCMOS structure for the bipolar PROM, it is advantageous to use a CMOS circuit for the address input circuit 2 because a low power consumption and a high-speed operation can be realized and there is study to employ the CMOS circuit for the address input circuit 2. But when the CMOS circuit is used for the address input circuit 2, problems occur since the input threshold value of the CMOS circuit changes when the power source voltage Vcc changes and the PROM writer is designed to operate with the TTL level.
In the case of the CMOS (or BiCMOS) address input circuit 2 which comprises a p-channel transistor Pch and an n-channel transistor Nch which are connected in series between the power source voltage Vcc and the ground GND as shown in FIG. 4A, for example, the input threshold value Vth is set to an intermediate voltage between the power source voltage Vcc and the ground. For example, this intermediate voltage is approximately Vcc/2. For this reason, the input threshold value Vth of the CMOS address input circuit 2 changes when the power source voltage Vcc changes.
FIG. 4B shows an equivalent circuit of the CMOS address input circuit 2. In FIG. 4B, the CMOS address input circuit 2 is illustrated as a series connection of two variable resistors Ra and Rb the resistances of which vary depending on the input voltage. An output voltage V.sub.OUT can be described b V.sub.OUT =Vcc.times.Rb/(Ra +Rb). For example, the input threshold value Vth of the CMOS address input circuit 2 can be set to approximately 1.4 V in the read mode but the input threshold value Vth increases to approximately 2.1 V when the power source voltage Vcc is increased in the write mode. But according to a typical TTL level, a low logic level is 0.8 V or less and a high logic level is 2.0 V or greater and the PROM writer is designed with this typical TTL level. As a result, even when an input voltage of 2.0 V which is a high logic level according to the TTL level is applied to the CMOS address input circuit 2 in the write mode when the input threshold value Vth is 2.1 V, the CMOS address input circuit 2 regards this input voltage as a low logic level since it is less than the input threshold value Vth as shown in FIG.5.
Therefore, the CMOS address input circuit 2 carries out an erroneous operation in the write mode in response to the input voltage which is set in conformance with the TTL level. Hence, the PROM writer which operates with the TTL level cannot be used when the CMOS address input circuit 2 is used because the TTL level cannot be discriminated correctly in the write mode. When the input threshold value of the CMOS address input circuit 2 is reduced in the write mode to enable a correct discrimination of the high and low logic levels in conformance with the TTL, it then becomes impossible to correctly discriminate the high and low logic levels in the read mode. For this reason, there is a problem in that the PROM writer must be designed to operate with the CMOS level if the CMOS address input circuit 2 is to be used. However, because virtually all of the existing PROM writers are already designed to operate with the TTL level, it would be extremely troublesome and expensive to design new PROM writers exclusively for the CMOS address input circuit 2 to make the same programming as the existing PROM writers.